1. Field of the Invention
The present invention relates to integrated circuit devices on semiconductor substrates, and more particularly to a method for fabricating N and P doped wells for field effect transistors, (FETs) and concurrently forming N and P doped field regions under the field oxide isolation regions on semiconductor substrates.
2. Description of the Prior Art
The density of field effect transistors (FETs) formed on integrated circuit chips diced from semiconductor substrates have dramatically increased in recent years. As the number and the density of transistors continue to increase on the chip the power consumption on the chip significantly increases. To avoid the heating effect on the chip and minimize the cooling requirements on these ultra larger scale integration (ULSI) circuits it is common practice in the electronics industry to rely on circuits that consume less power. One important circuit technology for minimizing the power consumption is the Complimentary Metal-Oxide-Semiconductor (CMOS) circuit. The CMOS circuits are typically formed from N-channel and P-channel FETs, and are particularly useful for the inverter circuit that form the basic building block for digital circuits, such as are used in computers and microprocessor.
Although the basic structure of early FETs used metal gate electrodes and silicon oxide gates on a silicon semiconductors, and where referred to as Metal-Oxide-Semiconductor FETs (MOSFETs), present day FETs are predominantly made with conductivity doped polycrystalline silicon (polysilicon) having decidedly better high temperature processing properties. However, it is still common practice in the industry to refer to the circuits made from these polysilicon gate electrode FET as CMOS circuits.
The P and N-channel FETs that comprise the CMOS circuit are, respectively, built on N and P doped wells that are formed in the top portion of the silicon substrate. The field effect transistors are electrically isolated from each other, usually by a relatively thick oxide formed on and in the substrate surface, referred to as the "field oxide" (FOX). It is a common practice in the semiconductor industry to form the field oxide by the method of LOCal Oxidation of Silicon (LOCOS). The LOCOS method involves forming a silicon oxide layer (pad oxide), usually by thermal oxidation of the substrate surface, and then depositing an oxidation barrier layer composed of silicon nitride. The silicon nitride layer is then patterned on the substrate using a photoresist mask and etching, exposing the substrate surface in the required field oxide areas while leaving portions of the nitride layer over the desired P and N-well areas. Prior to removing the photoresist mask a channel stop implant is usually formed in the exposed areas, and then after removing the photoresist the substrate is thermally oxidized to form the field oxide. The channel stop implant prevent inversion of the silicon surface under the field oxide, and thereby preventing electrical leakage currents between the isolated well regions. Typically, separate photoresist masking and ion implantation steps, either prior to or after forming the field oxide are required to form the P and N doped wells. Unfortunately, these additional masking and implant steps result in increased manufacturing cost and decreased yield.
A method for providing a field oxide with improved channel stop implants is described by C. W. Teng et al, U.S. Pat. No. 4,987,093, for both N and P-wells. However, methods for merging or integrating the process steps for forming the channel stop region and the well regions is not described.
There is still a strong need in the semiconductor industry for improving the CMOS semiconductor device process while providing a cost effective manufacturing processing.